Data processing system having a function of changing a bus width.

摘要

In a microcomputer, a high-order address bus 34 of a CPU 31 is coupled to a first input of an address selector 40 and an address latch 38 having an output coupled to a second input of the address selector 40. An output of the address selector is connected to one input of a multiplexer 41 having the other input connected to a high-order data bus 32 of the CPU and an output connected to high-order address/data bus terminals 3. In the case that the microcomputer is coupled to only 8-bit external memories, the high-order address is outputted through the high-order address/data bus terminals 3 during a period of accessing to the external memory, and the address latch 38 and the address selector 40 are controlled to output the high-order address latched in the address latch 38 through the high-order address/data bus terminals 3 during a period of executing no access to the external memory. <IMAGE>