| 摘要 |
A semiconductor memory device capable of storing a plurality of bits at the same address and of reducing a test time without increasing the number of pins includes comparing circuits located between a plurality of memory cell blocks from which data at the same address is read, and an input/output pin used in ordinary operations for reading and writing data. The comparing circuits serve to detect coincidence and non coincidence of the data from the memory cell blocks and the pin. Preferably, there is provided a logic for superposing outputs of the comparing circuits. An error flag signal supplied from the superposing logic is transmitted through a no-connection pin, thereby reducing the number of pins. |
