发明名称 |
Semiconductor integrated circuit |
摘要 |
A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).
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申请公布号 |
US5422858(A) |
申请公布日期 |
1995.06.06 |
申请号 |
US19940260894 |
申请日期 |
1994.06.16 |
申请人 |
HITACHI, LTD.;HITACHI ULSI ENGINEERING CORP. |
发明人 |
MIZUKAMI, MASAO;SATO, YOICHI;KOZAKI, TAKAHIKO;SHINAGAWA, SATOSHI |
分类号 |
G06F1/04;G06F1/10;G06F15/78;G11C8/16;G11C11/401;G11C11/407;G11C11/41;(IPC1-7):G11C8/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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