| 摘要 |
<p>A speech information processor includes a first execution device (CPU (1)) and a second execution device (DSP (6)) for executing operations at respective different execution cycles, and a first memory (2) for reading and recording speech information. The CPU (1) and the DSP (6) exploit the first memory (2) in common for processing the speech information. The processor further includes a second memory (FIFO (3)) for storage of speech information from the CPU (1) or speech information read out from the first memory (2). The CPU (1) records the speech information on or reads the speech information from the second memory (3) during the execution cycle of the CPU. The DSP (6) accesses the first memory (2) during the execution cycle of the DSP for outputting the speech information to outside. The speech information recorded in the second memory (3) is read out and recorded in the first memory (2), or the speech information recorded in the first memory is read out and recorded in the second memory during the time of not accessing the first memory. Data transfer between the CPU (1) and the second memory (3) can be performed during the execution cycle of the CPU, while that between the second memory and the first memory (2) can be performed during the execution cycle of the DSP (6), so that it is possible for the CPU to perform data transfer independently, such that sound source data can be transferred at a higher speed by employing a high-speed device as the CPU. <IMAGE></p> |
