| 摘要 |
PURPOSE:To reduce power consumption by generating a VC synchronizing signal when an SPE address and an internal pointer are coincident in the pointer processing in an inter-network interface so as to reduce the circuit scale. CONSTITUTION:A pointer processing circuit 1 is provided with a counter 60 implementing counting synchronously with a virtual container VC in a received STM frame. When the STM frame is a non-stuffed frame, a register 40 generates an internal pointer CP based on a content of an overhead. A synchronizing pulse generating section 50 generates a VC synchronizing signal VCFP representing a head of the VC through the coincidence detection between an SPE address PAY and the pointer CP and generates a VCFP through the detection of reset of the counter 60 when the STM frame is a stuffed frame. When the STM frame is a non-stuffed fame, load control to the counter 60 is implemented corresponding to the coincidence detection between the address PAY and the pointer CP independently of the pointer CP. |
