| 摘要 |
In a flash EEPROM where erasing and verifying operations are repeated until the threshold voltages of memory cells reach a predetermined value, a negative voltage is applied, at the time of verification, to the control gate electrode of each cell on a nonselected row, so that the verification is rendered possible despite the existence of any overerased memory cell in the nonselected area, and then the overerased cell is rewritten to be released from the overerased state, whereby the threshold voltage distribution of the memory cells is settable in a narrow range. And by the provision of a means for converting an external designated address to an internal chip address, the storage area designated by the external address is shifted or circulated in the chip every time the data is erased, so that the number of repeatable reprogramming actions is increased apparently in the flash EEPROM. <IMAGE> |
