SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PURPOSE:To provide a semiconductor integrated circuit device having memory cells of full CMIS structure in which the degree of integration is increased by reducing the cell size of memory cell. CONSTITUTION:The p-channel conductivity type load MISFETs Qp1 (or Qp2) in a plurality of memory cells 7A arranged in the column direction are formed in an n-type well region 13 along the extending direction of word line WL. The source region of the load MISFET Qp1 in the memory cell 7 is connected electrically with the n-type well region 13 through a conductor layer 23A formed independently from the plurality of memory cells 7A arranged in the column direction.