发明名称 DEBUGGING SYSTEM FOR INFORMATION PROCESSOR FUNCTION TEST PROGRAM
摘要 PURPOSE:To eliminate countermeasure by a manual operation and to highly efficiently execute debugging by debugging a function test program through the use of an information processor different from the information processor of a test object. CONSTITUTION:The operation fo the information processor consisting of an instruction processor 23, a main storage device 21 and an input/output device 27 is verified by loading the function test program on the main storage device and making the instruction processor 23 to execute it. The function test program is debugged by using the information processor different from the information processor which the function test program sets to be the test object. Abnormal termination interruption is adopted and an instruction having become abnormal termination and an operation on the architecture of the input/output device 27 are simulated on abnormal termination owing to the issuing of a generated non-support instruction and the designation of the input/output device. Furthermore, a means for automatically re-executing the operation from an interruption- occurred place is provided so as to execute the function test program.
申请公布号 JPH07105045(A) 申请公布日期 1995.04.21
申请号 JP19930246593 申请日期 1993.10.01
申请人 HITACHI LTD;HITACHI COMPUTER ELECTRON CO LTD 发明人 OTA HARUHITO;TASHIRO JUNICHI
分类号 G06F11/28;G06F11/22 主分类号 G06F11/28
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