发明名称 FEEDTHROUGH SUPPRESSION CIRCUIT
摘要 <p>PURPOSE:To provide a circuit for suppressing wide band feedthrough. CONSTITUTION:In a CW radar having a phased array antenna, the transmission interval is repeated while interposing a pause period for switching the beam. Switches 1, 2 switch an input signal between a feedthrough receiving period present in the initial stage of receiving period and a following target signal receiving period. During the feedthrough receiving period, detecting circuits 3-6 detect a feedthrough and low frequency components extracted by LPFs 7, 8 are digitized by ADCs(A/D converters) 9, 10 and then averaged by adders 11, 12 and memories 13, 14 to produce a suppression data being stored. During a target signal receiving periodal, the suppression data is taken out from the memories 13, 14 and converted by DACs(D/A converters) 15, 16 into an analog data, and a suppression signal is produced in weighting circuits 17-20. It is fed to an adder 21 which outputs a receiving data subjected to feedthrough suppression.</p>
申请公布号 JPH0777572(A) 申请公布日期 1995.03.20
申请号 JP19930247464 申请日期 1993.09.08
申请人 JAPAN RADIO CO LTD 发明人 TAMURA HIDEKI
分类号 G01S7/02;G01S13/32;(IPC1-7):G01S7/02 主分类号 G01S7/02
代理机构 代理人
主权项
地址