ATM SWITCH

摘要

PURPOSE:To avoid the limit of a transfer rate based on a difference from a wiring length by reading cells from an input buffer in a timing in response to the wiring length difference and taking bit synchronization for each output line. CONSTITUTION:Cells inputted from input lines 101-104 are stored in input buffers 21-24. A cell read timing generating circuit 1 generates a read timing and transfers it to the buffers 21-24 via signal lines 61-64. The buffers 21-24 send cells at their own period and cells are sent among the adjacent buffers 21-24 at a deviated time. An operating timing of each switch in cross points 511-544 is set in following to or synchronously with the circuit 1. A cell is transferred in a switch network 50 without bit synchronization and inputted to bit synchronization circuits 301-304, in which synchronization is taken. The circuits 301-304 uses plural or one clock with a predetermined frequency from signal lines 401-404 to take bit synchronization of cells from signal lines 111-114 and output cells after bit synchronization to output lines 201-204.