| 摘要 |
<p>Data transfer efficiency is improved by making a bus transfer protocol programmable and by providing on a bus of a predetermined bit width a plurality of data with a bit value smaller that the bit width in one cycle under a programmed operation. A draw control chip (10) and video chips (V1 - V4) are provided. They are connected by a 64-bit data bus (20), a 4-bit program signal line (22), and a 1-bit ready signal line (24). The video chip (V1) comprises a decoder (DEC1), a program buffer address register (PBAR), a sequencer (SEQ), a program buffer (PB), a decoder (DEC2), an address control unit (54), a selector (SEL), and various registers. The video chip (V1) and the video buffer (APA1) are connected by the data bus (20). <IMAGE></p> |
