发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS INSPECTING METHOD
摘要 PURPOSE:To make self-diagnosis possible at a high speed with simple constitution by connecting a data forming means and a data comparing means to buses connected to memories at the time of inspecting these memories. CONSTITUTION:The data pattern formed by the data forming means 31 is outputted to the instruction bus 100 and the data bus 200, in written in the tag memories 14, 24 and the tag parts of the addresses from address forming means 11, 12 are respectively written in parallel in the tag memories 15, 25. The data read out of a bank 13 or 23 in the one bus and the expected value from the data forming means are then compared by the comparing means 32. The expected value from the tag memory 15 or 25 and the tag parts of the addresses from the address forming means 11, 21 are compared by the tag comparing means 16 or 26. The bits corresponding to the data memories 14, 24 or the tag memories 15, 25 are set if no coincidence exits between the expected value and the data. As a result, the self-diagnosis of the memories is performed without requiring the supply of the addresses and data from the outside.
申请公布号 JPH0745099(A) 申请公布日期 1995.02.14
申请号 JP19940083109 申请日期 1994.04.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MAEDA TOSHINORI;WATARI SHIGERU
分类号 G06F12/08;G11C29/00;G11C29/02;G11C29/12;G11C29/34;G11C29/56;H01L21/66 主分类号 G06F12/08
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