| 摘要 |
A floating gate memory device (10) comprises a channel (18) for conducting carriers from source (12) to drain (14), a semiconductor heterostructure (20) forming a potential well 24; (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region (20.2) between the control gate (16) and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Array of memory devices may also be used to detect light in a variety of applications such as imaging. |
