| 摘要 |
A semiconductor memory device of alternately-activated open bit-line architecture is provided wherein paired bit lines extend from opposite sides of sense amplifiers that are arranged in one direction and every other bit line is activated through activation of a word line intersecting the bit lines. The sense amplifiers in the neighboring first and second rows alternate with each other in a staggering manner. The bit lines extending from the sense amplifiers of the first row in a first direction and the bit lines extending from the sense amplifiers in the opposite, second direction constitute a bit line group between the first and second rows. Word lines and dummy word lines intersect the bit line group. In operation, signals opposite in phase to each other are applied to a selected word line and a corresponding dummy word line from a control section so that memory cells connected to the selected word line are electrically connected with the bit lines while the dummy cells connected with the same bit lines are electrically disconnected from these bit lines.
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