发明名称 |
VIDEO COMPRESSION EXPANSION CIRCUIT |
摘要 |
PURPOSE:To obtain a video image in matching with an aspect ratio of a screen of a display device by reducing/magnifying an entire video image into an optional size. CONSTITUTION:A video signal is written sequentially in a field memory 103 by a write clock from an input terminal 118. A clock generating circuit 119 gives a read clock whose frequency is nearly a multiple of 4/3 of a write clock frequency to a field memory 103. A vertical magnification control circuit 110 reads a video signal from the field memory 103 by a line period in response to the magnification factor. The write of a 1-line memory 105 is stopped by a similar period to obtain a line delay output of an output signal from the field memory 103. A vertical interpolation circuit 106 generates a scanning line signal through interpolation arithmetic operation according to a control signal from the vertical magnification control circuit 110. |
申请公布号 |
JPH077723(A) |
申请公布日期 |
1995.01.10 |
申请号 |
JP19930146674 |
申请日期 |
1993.06.18 |
申请人 |
HITACHI LTD;HITACHI GAZO JOHO SYST:KK |
发明人 |
KATSUMATA KENJI;HIRAHATA SHIGERU;MURATA TOSHINORI;TAKADA HARUKI;TORIGOE SHINOBU;EDA TAKANORI;ISHIBASHI KOICHI |
分类号 |
H04N5/262;H04N3/27;H04N5/46;H04N7/01 |
主分类号 |
H04N5/262 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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