Distributed clock signal and clock signal interrupt

摘要

A clock distribution system and clock interrupt system provides clock signals with less than 100 picoseconds of skew to various components of an integrated circuit 200 (ignoring effects associated with the matched stages) by using several stages of drivers 301, 310 - 314, 30a - 30l to evenly supply the distributed clock signals. Each stage has RC matched input lines e.g. 340 - 344. The matched stages and clock drivers are located within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The drivers can be selectively powered downs in groups by a power management unit.