发明名称 Sample-and-hold circuit device
摘要 A sample-and-hold circuit device which includes a plurality of sample-and-hold circuits and a comparator/amplifier for comparing a reference potential with an output signal which is output from the plurality of sample-and-hold circuits so as to amplify a difference between these two signals. An output of the comparator/amplifier is fed back to respective control terminals of the different sample-and-hold circuits, each being provided as a level control signal. In another embodiment, a plurality of adding circuits are provided for adding the outputs of the plurality of sample-and-hold circuits and then comparing this value with an arbitrary reference potential, whereby a difference between the sum value and the arbitrary reference potential is amplified and fed back to the control terminals of the sample-and-hold circuits.
申请公布号 US5376841(A) 申请公布日期 1994.12.27
申请号 US19930143127 申请日期 1993.10.29
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ITAKURA, TETSURO;SHIMA, TAKESHI
分类号 G09G3/36;G11C27/02;(IPC1-7):H03K5/153;H03K5/24 主分类号 G09G3/36
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