| 摘要 |
PURPOSE: To provide a circuit arrangement generating a clock signal for automatically correcting the situation of false synchronization. CONSTITUTION: This system includes a controllable clock signal source 1 and the polarity deciding circuit 8 of two phase signals at two consecutive sampling time point in a single symbol division. In addition, a phase detector 35 including the first comparator 16 of polarity at two sampling time points to generate a control signal adjusting the frequency and the phase of a controllable clock signal source according to its output signal. In addition, circuit arrangement includes the second comparator 28 of polarity at the two sampling time point. The second comparator prohibits a phase detector 35 according to this output signal. At the time of false synchronization, the output signal of the detector 35 keeps giving the same signal value and its result is automatically adjusted to make the time point of correct synchronization. Adjusting is executed by VCO 3 and a phase shift means 12. |
