| 摘要 |
PURPOSE:To generate a status signal without using output data from an amplitude limiting circuit, to suppress speed reduction due to the delay of the amplitude limiting circuit and to speed up processing. CONSTITUTION:At the time of receiving an input data 14, an arithmetic circuit 17 executes operation in accordance with a control signal 12 outputted from a decoder 13 receiving an arithmetic instruction 11 and outputs its operation result to the amplitude limiting circuit 18 and a flag generating circuit 20. The circuit 18 outputs an input as it is in accordance with a control signal 16 outputted from the circuit 17 or converts the input into a positive or negative maximum value and outputs the converted maximum value as output data 21 from this arithmetic unit. Simultaneously the circuit 20 outputs a status signal 19 for the arithmetic unit in accordance with the output data 15 of the circuit 17 and the control signal 16 from the circuit 17. |
