| 摘要 |
PURPOSE:To lower the probability of the occurrence of defects when a defective word or bit line is switched to a standby word or bit line so as to improve the operating margin of a semiconductor storage device by providing standby bit or word lines at nearly the central part of the memory mat of the storage device. CONSTITUTION:Word lines WL0-WLn are arranged in parallel in the longitudinal direction. Paired complementary bit lines, the one ends of which are connected to paired input-output nodes of sense amplifiers SA, are arranged in parallel in the transversal direction. The complementary bit lines BL1T and BL1B having odd numbers having twist sections in which the arrangement of the lines are changed to each other at their central parts. In addition, two standby word lines RWL0 and RWL1 are provided at the left-side central parts of the twist sections and two standby word lines RWL2 and RWL3 are provided on the right-side central parts. As a result, the occurrence of defects at the central part of a memory mat is relatively reduced against the occurrence of defects at edge sections. Therefore, the defect remedying probability when a normal word line is switched to a standby work line without tests due to a defect can be improved. |
