| 摘要 |
<p>PURPOSE:To obtain a serial bus communication system capable of constituting a slave side only of logic circuits by putting a trigger pulse on the head of every bit cycle. CONSTITUTION:The communication of information is performed by a pulse width modulation between a master-side transmission system 2 having a master transmission logic 4 and a master reception logic 6 and a slave-side transmission system 3 having a slave transmission logic 18 and a slave reception logic 16. In this system, each transmission logic outputs a trigger pulse of 1/4 bit cycle width, for instance, on the head of every bit cycle of information to be transmitted and succeedingly puts data on the head. Each reception logic latches data when 1/2 bit cycle, for instance, passes after prescribed period passes from the front end of a trigger pulse. Thus, a slave side can be assembled only with logic circuits.</p> |
