| 摘要 |
<p>According to the present invention, faulty isolated bits in the cache memory are made inaccessible to the microprocessor by rendering an appropriate line of data in the cache memory uncacheable to the microprocessor. When faulty data bits are not repairable through conventional repair means such as row/column redundancy, the tag RAM may be programmed with the address of the faulty data bit such that when the microprocessor requests data at that address, a comparator inside the tag RAM generates a signal indicative of a "miss" condition which is an output signal of the tag RAM. The miss condition is communicated to the microprocessor which must access the requested data from main memory. In this way, a cache memory having faulty data bits may still be utilized. <IMAGE></p> |
