发明名称
摘要 PURPOSE:To add a characteristic while a mantissa is multiplied by using the whole adding circuit of a part of a fixing point multiplying circuit by adding a multiplexer. CONSTITUTION:When multiplier characteristic data and multiplicand characteristic data are selected by a multiplexer 24, the adding of the characteristic is executed by a whole adding circuit 25 and the adding result is inputted and latched to a register 26 by a characteristic adding data signal line 30. On the other hand, when the multiplexer selects the data from a mantissa intermediate data high-order signal line 17 and a carrying signal line 18, the multiplying calculation of the final step of the high-order digit of mantissa data is executed by the whole adding circuit 25. Namely, the circuit composed of a decoder 21, an array circuit 22 of the multiplexer and the whole adding circuit, whole adding circuits 23 and 25 and the multiplexer 24 comes to be the function of the fixing point multiplying circuit. The changing-over of the signal input of the multiplexer 24 is executed by the time division.
申请公布号 JPH0697432(B2) 申请公布日期 1994.11.30
申请号 JP19860140679 申请日期 1986.06.17
申请人 发明人
分类号 G06F7/487;G06F7/52;G06F7/53;G06F7/533 主分类号 G06F7/487
代理机构 代理人
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