Method and arrangement for the interference-free clock recovery for digital signals having a constant bitrate at the receiving end

摘要

The solution according to the invention is used for the interference-free, i.e. as jitter-free as possible recovery of the clock of a transmitting device, operated at a constant bitrate, in the receiving terminal. According to the invention, the incoming cells, having in each case 47 useful bytes, are combined to form periods having the same number of useful byte cells in the cell demultiplexer during the clock recovery. To each period of useful-byte cells, the combination of two combinations of blank-byte groups differing in the total sum of their bytes are combined in dependence on the loading of the splitter memory, which combination, on the one hand, results in a good clock frequency adaptation to the terminal and, on the other hand, in a uniform distribution of the blank-byte groups, the sums of the bytes of which differ, over the entire period. Since it is possible to achieve a very small deviation from the terminal clock frequency by means of the solution according to the invention, it is possible to make the subsequent circuit for clock recovery highly inert with respect to its lower cut-off frequency.