发明名称 VARIABLE DELAY CIRCUIT
摘要 <p>PURPOSE:To easily change the setting of a delay amount. CONSTITUTION:Plural delay units are constituted in the memory space of a delay memory 20. For the reason, the initial values of plural sets of write addresses and read addresses, the step amount of address, a bottom address and a top address are loaded in the memory 21. These address values are read out from the memory 21, and the delay memory 20 is address controlled. The write addresses are made to precede and both the write addresses and the read addresses are changed stepweise based on clocks with the same frequency. By that the change in the read addresses are fixed to one step and the step amount of the change in the read addresses is set to any one of 0, +1, +2, the control of the increase of the delay amount, the fixation of the delay amount and the decrease of the delay amount are performed.</p>
申请公布号 JPH06318092(A) 申请公布日期 1994.11.15
申请号 JP19940110463 申请日期 1994.04.26
申请人 SONY CORP 发明人 SEKIGUCHI KEISUKE;ISHIZAKA KOICHI
分类号 G10K15/12;H03H17/02;H03H17/08;H03K5/13 主分类号 G10K15/12
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