发明名称 LOOP FILTER FOR PLL CIRCUIT
摘要 PURPOSE:To reduce a time till locking and to reduce noise of the system when locking takes place by charging a capacitor through which one terminal of a resistor is connected to ground via a charging line when a voltage drop of the resistor inserted in series between a phase comparator and a voltage controlled oscillator reaches a predetermined value or over. CONSTITUTION:An oscillated frequency of a VCO 1 is frequency-divided by a frequency divider circuit 2, a phase of an output of the frequency divider circuit 2 is compared with a phase of an input signal at the phase comparator 3, a DC component of a phase comparison output is extracted by a lag/lead loop filter 4A and fed to a voltage controlled oscillator 1 as a frequency control voltage. When a voltage across a resistor 41 inserted in the loop filter 4A reaches a predetermined voltage or over, a transistor(TR) 45 is turned on and a capacitor 43 is charged from a DC power supply Vcc through resistors 47, 42. When the charging is advanced and the voltage across the resistor 41 decreases less than the predetermined voltage, the TR 45 is turned off and charging from the DC power supply Vcc is stopped.
申请公布号 JPH06314971(A) 申请公布日期 1994.11.08
申请号 JP19930124811 申请日期 1993.04.30
申请人 KENWOOD CORP 发明人 IIZUKA NOBUO
分类号 H03L7/093;H03L7/107 主分类号 H03L7/093
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