| 摘要 |
<p>PURPOSE: To provide series interface processing method/device for reducing control pins in CPU and for simplifying electric line connection. CONSTITUTION: In CPU interface processing, a mix series signal containing a data pulse signal and a trigger signal, which are alternately outputted by CPU 41, is converted into a trigger(TGR) signal separated from parallel data signals D0-D7 and the mix series signal by a series-parallel data conversion processing and a debounce processing. Thus, the number of the pins connected with a prescribed peripheral circuit device 43 of CPU 41 can considerably be reduced.</p> |
