| 摘要 |
PURPOSE:To provide a PLL circuit having a triplex loop structure having advantages of both the analog phase control improving the C/N and the digital phase control for broad band locking and increasing a comparison frequency in a simulating way. CONSTITUTION:The PLL circuit is provided with a VCO 23, a 1st digital feedback signal generating means 24, a 2nd digital feedback signal generating means 25, a high frequency analog reference signal generating means 31 multiplying an analog reference signal, means 27, 28 generating a 1st phase error signal from the 2nd digital feedback signal and the digital reference signal, means 29, 30 adding a phase error signal between the 2nd digital feedback signal and the analog reference signal to the 1st phase error signal to generate a 1st synthesis phase error signal, means 34, 35 adding a phase error signal between the 1st digital feedback signal and the high frequency analog reference signal to the 2nd phase error signal to generate a DC control voltage. |
