Semiconductor memory device having redundant memory cells

摘要

The described embodiments of the present invention provide a method in which the circuit configuration of redundancy circuitry in a random access memory can be simplified and the setting operation of the address of the defective memory cell is also simplified. In one described embodiment, the redundant circuit includes a fuse decoder (11), which functions as the address-generating circuit for the address of the defective memory cell, and a latch circuit (21). A write operation to the defective memory cell on the write port containing the fuse decoder (11) causes the address of the defective cell to be stored in the latch circuit. Each input/output port, except the input port using the fuse decoder, includes a comparator (22) for comparing the address for an operation on the respective port to the address stored in the latch circuit. A timing logic circuit (23) responds to a coincident signal generated by the comparator by providing signals which enable access to the redundant memory cell rather that the defective memory cell.