| 摘要 |
<p>A signal processor, which includes a plurality of signal processing circuits, outputs predetermined data passing sequentially through the signal processing circuits. The timing necessary for operation in the individual signal processing circuits is added as header information to the data transferred. In this way, the present invention makes it possible for each signal processing circuit to reliably process the data and to transfer the data while avoiding a complicated construction including a timing circuit for signal processing by each signal processing circuit.</p> |
