| 摘要 |
PURPOSE:To eliminate a rounding error at the time of product sum arithmetic without increasing the processing time of the product sum arithmetic, data transfer, etc. CONSTITUTION:In the latter half of the cycle right before a cycle wherein arithmetic and logic operation using the high-order side bit MSBH of the multiplication result of a parallel multiplier 4 as one input is performed, the low-order side bit LSBH of the multiplication result is inputted to a low-order side arithmetic and logic computing element 10 independent of a high-order side arithmetic and logic computing element 9 together with the low-order side output of a register (accumulator) 11; and the low-order side arithmetic and logic operation is completed in the half cycle, and a carry signal from the low-order side arithmetic and logic computing element 10 is prepared in the beginning of a cycle wherein high-order side arithmetic and logic operation is performed and then used to perform the high-order side arithmetic and logic operation by a high- order side arithmetic and logic computing element 9. |
