| 摘要 |
In a word line driving circuit coupled to a word line of a memory cell array of a semiconductor memory device, a first transistor has a first terminal receiving an input signal based on a row address signal applied to the semiconductor memory device, a second terminal, and a control terminal receiving a first timing signal. A second transistor having a first terminal receiving a second timing signal, a second terminal connected to the word line, and a control terminal connected to the second terminal of the first transistor. A third transistor has a first terminal connected to the second terminal of the second transistor, a second terminal set at a predetermined potential, and a control terminal receiving a third timing signal. The first transistor has a threshold voltage less than that of at least one of the second and third transistors.
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