| 摘要 |
PURPOSE:To correct fluctuation in the timing skew caused by various factors. CONSTITUTION:The delay of a variable delay circuit 16 is controlled based on a timing correction data outputted from a memory circuit 23. Address from the memory circuit 23 is connected with the outputs of a clock type control 20, a period control 21, a timing control 22 for controlling the clock type, period, and timing being used in the generation of driver output timing and strobe acquisition timing, the output of a pattern buffer 14 for storing a test data pattern, and the output of a wave control 19 for designating the output waveform of data. Each address stores a corresponding data pattern, a waveform, a clock type, a period, and a timing correction data representative of an appropriate delay for the timing. |
