| 摘要 |
<p>A very large scale, read-only memory which is read by selectively discharging bit lines (30(i)) and virtual ground lines (32(i)) is read at subtantially higher speeds by precharging the bit lines and virtual ground lines of memory core (10) at both the top and bottom of the memory core at opposing ends of bit lines and virtual ground lines. The memory core is precharged using a precharge decoder (28) which provides upper and lower address precharging signals timed on sequential clocks. The precharge decoder is selected to precharge sectors of the memory core by the address signals of the memory core. A precharge decoder is provided for each sector of the memory core so that the entire memory core is precharged in this manner.</p> |
