| 摘要 |
PURPOSE:To provide a crash detector in which the detection lag of crash can be minimized at low cost. CONSTITUTION:Two CPUs 14, 16 read in the output value S from a crash sensor and operate the output value S to decide crash. The CPU 16 reads in the output value S with a predetermined short time lag DELTAT shorter than one cycle T of crash decision processing as compared with the CPU 14 and when the CPU14 is operating an output value Sk to decide crash, the CPU 16 reads in an output value Sk+1. Consequently, detection lag of crash can be minimized. Furthermore, read-in blank time can be shortened using an inexpensive CPU just like a case employing a CPU having high operating speed. An external memory for storing data of the CPUs 14, 16 is constituted of a common memory which can input and output data to and from both CPUs. Since the output value S is read by both CPUs 14, 16 and employed for deciding crash, crash detection accuracy is enhanced. |
