发明名称 PHASE COMPARATOR CIRCUIT IN BIT CLOCK SIGNAL GENERATOR FOR DIGITAL SIGNAL DEMODULATION
摘要 PURPOSE:To simplify the generator and to attain superior phase comparison even when a bit rate of a demodulated signal is changed by outputting a specific signal including a phase error signal only for a period set by the phase error signal. CONSTITUTION:A demodulated signal Sd fed to an input terminal 2 is fed to a data terminal of a D flip-flop(DFF) 5 and fed to an exclusive OR circuit(EXOR) 6 and its output signal is used as an output period setting signal Sp of a phase error signal. The signal Sp is fed to a clock terminal of the DFF 7 and fed to a switch circuit 9 as a switching control signal. An output signal from an EXOR 8 receiving an output signal from the DFF 7 is fed to an output terminal 4 as a phase error signal via the switch circuit 9 and the switch circuit 9 is turned on only when the output period setting signal Sp is on a high level. Thus, a window pulse generating means for phase comparison in a phase comparator circuit 1 is not required.
申请公布号 JPH06216892(A) 申请公布日期 1994.08.05
申请号 JP19930023272 申请日期 1993.01.18
申请人 VICTOR CO OF JAPAN LTD 发明人 HAYAMIZU ATSUSHI
分类号 G11B20/14;H03M5/06;H04L7/033 主分类号 G11B20/14
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