发明名称 HIGH-SPEED AND LOW-GATE/DRAIN CAPACITANCE P-MOS DEVICE
摘要 PURPOSE: To provide a newly improved high speed gate/drain capacitance DMOS device. CONSTITUTION: This is a DMOS device 30 provided with impurities 44 to be implanted through the same aperture which is used when the field oxide layer 46, to be formed in the channel between the adjacent transistors, is formed. A gate 50 is deposited on the field oxide layer 46, the gate 50 is separated from a supporting epitaxial layer 34 by the field oxide layer 46, and gate/drain capacitance is decreased. The ON resistance of the device 30 is decreased by the impurities implanted on the field oxide 46.
申请公布号 JPH06204484(A) 申请公布日期 1994.07.22
申请号 JP19930230748 申请日期 1993.08.25
申请人 MOTOROLA INC 发明人 HAKU YAMU TSUOI
分类号 H01L21/336;H01L29/08;H01L29/423;H01L29/78;(IPC1-7):H01L29/784 主分类号 H01L21/336
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