发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY CAPABLE OF ELECTRICAL WRITING AND ERASING
摘要 <p>PURPOSE:To reduce variation in erasing speed in erasing operation when a redundant cell array group is used. CONSTITUTION:In order to equalize levels of voltage applied to a source of a redundant cell and a source of an ordinary cell in erasing operation, transistors T11 and T12 applying erasing voltage are mounted every specified number of transistors, then performance for supplying erasing voltage to the redundant cell and the ordinary cell are equalized. And a redundant function is made optimum by coinciding erasing speed of the ordinary cell with that of the redundant cell in erasing operation.</p>
申请公布号 JPH06203583(A) 申请公布日期 1994.07.22
申请号 JP19930000925 申请日期 1993.01.07
申请人 NEC CORP 发明人 SATO TOSHIYA
分类号 G11C17/00;G11C16/02;G11C16/06;G11C16/16;G11C29/00;G11C29/04;(IPC1-7):G11C16/06 主分类号 G11C17/00
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