| 摘要 |
A processor arrangement (SX,BP1,BP2,ADS,PERS/ DX, BP3,BP4,ADD,PERD) with a processor (SX/ DX), a peripheral circuit (PERS/ PERD) and a processor interface (BP1,BP2,AD/ BP3, BP4,AD2) between them including a conversion device (ADS/ ADD), is disclosed. The conversion device (ADS/ ADD) converts address and data bus control signals of the processor (SX/ DX) to address and data bus control signals suited for the peripheral circuit (PERS/ PERD). The conversion device (ADS/ ADD) is built from multiplexers and has a disable input (ENADS/ ENADD) allowing it to be put in a high impedance state without giving rise to timing problems, even when used in combination with a high speed processor (SX/ DX). <IMAGE>
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