发明名称 |
Manufacturing process for a micro MIS type FET |
摘要 |
A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 mu m, a second conductivity type channel layer having an impurity concentration of less than 1x1016/cm3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1x1017/cm3 beneath the channel layer.
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申请公布号 |
US5330923(A) |
申请公布日期 |
1994.07.19 |
申请号 |
US19920980408 |
申请日期 |
1992.11.20 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KUSUNOKI, SHIGERU;KOMORI, SHIGEKI;TSUKAMOTO, KATSUHIRO |
分类号 |
H01L29/78;H01L21/265;H01L29/10;(IPC1-7):H01L21/265 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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