发明名称 MULTILEVEL MULTIPLIER
摘要 PURPOSE:To share plural multilevel signals by means of setting a bit signal to be a multilevel without enlarging a circuit scale by providing logic circuit means and multilevel circuit means which are connected to the logic circuit means and output the prescribed multilevel signal based on a logical result. CONSTITUTION:A ternary multiplier consists of AND circuit elements (AND elements) 11-26 be ing the logic circuit means, multilevel function elements 27-78 being the multilevel circuit means, AND circuit elements (AND elements) 79-84, OR circuit elements (OR elements) 85 and 86, AND circuit elements (AND elements) 87-89, OR circuit elements (OR elements) 90-92, a one-bit delay circuit 93 and input/output elements 94-110. The AND element 11 inputs binary input signals Xo, Yo, xo and yo and outputs AND, for example. The multilevel function element 27 inputs output from the AND element 11 and outputs a ternary threshold. The multilevel function element 28 inputs output from the AND element 11 and outputs a binary threshold.
申请公布号 JPH06195204(A) 申请公布日期 1994.07.15
申请号 JP19930255380 申请日期 1993.10.13
申请人 SHARP CORP 发明人 YOSHIDA YUKIHIRO
分类号 G06F7/52;B82B1/00;G06F7/501;G06F7/523;H03K19/20 主分类号 G06F7/52
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