| 摘要 |
A multiplier containing first and second quadritail cells. The first quadritail cell has a first pair of first and second transistors, a second pair of third and fourth transistors, and a first constant current source for driving the first and second pairs. The second quadritail cell has a third pair of fifth and sixth transistors, a fourth pair of seventh and eighth transistors, and a second constant current source for driving the third and fourth pairs. Each of the first to fourth pairs has output ends coupled together. A first input voltage is applied between input ends of the first and fourth transistors and is applied between input ends of the fifth and eighth transistors. A second input voltage is applied between input ends coupled together of the second and third transistors and the input ends coupled together of the sixth and seventh transistors. The output ends of the first and fourth pairs are coupled together to form one of differential output ends, and those of the second and third pairs are coupled together to form the other of the differential output ends thereof. At least one of the first and second input voltages can be expanded in linear range at a low power source voltage such as 3 or 3.3 V. <IMAGE> |
