| 摘要 |
A phase detector circuit, used in a very high frequency phase-locked loop, receives an incoming NRZI data stream and a phase-locked loop clock signal. For each data transition in the received data stream, the phase detector produces proportional phase error information in the form of two pulse signals PD1 and PD2. Pulse signal PD1 has a pulse width TW1 which corresponds to the amount and direction of any phase error between the data signal transition and the PLL clock signal. Pulse signal PD2 has a fixed width TW2 equal to half the period of the PLL clock signal. The phase detector also generates a recovered data signal and a recovered clock signal using identical parallel circuits so that the recovered signals are time synchronized. Furthermore, the recovered data signal is derived from signals in the phase error detection path, eliminating the need for two distinct circuits for data recovery and clock recovery. In the preferred embodiment, the pulse signals from one positive and one negative data transition are integrated or averaged so as to eliminate problems associated with any duty cycle distortion and/or jitter in the incoming data stream. The sign and magnitude of the difference in the widths of the averaged pulse signals are proportional to the average phase error between the incoming data signal and the PLL clock signal.
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