发明名称 CIRCUIT DETERIORATION SIMULATION METHOD
摘要 <p>PURPOSE:To reduce the number of simulations, to know how each transistor's deterioration affects a circuit, and to shorten the time required to search how the transistor deterioration affects the circuit. CONSTITUTION:A circuit deterioration computing step 11 takes in analysis results before and after the deterioration from an analysis result tile 8 before deterioration and an anlysis result file 6 after deterioration. A computing point storage section 13 takes out the information of a computing point, passes the difference of the analysis results before and after the deterioration to a display step 12. The step 12 displays the circuit deterioration information (the intensity of fluctuation of contact potential and the list of transistors to be connected to the contact) based on the deterioration information of a deterioration list file 7, the computing result from a circuit deterioration computing section 11, and the connection information of the file 6. The section 13 stores the information on the contact to be prepared.</p>
申请公布号 JPH06168293(A) 申请公布日期 1994.06.14
申请号 JP19920321732 申请日期 1992.12.01
申请人 NEC CORP 发明人 NAKATANI YUKA
分类号 G06F17/50;G06F19/00;(IPC1-7):G06F15/60;G06F15/20 主分类号 G06F17/50
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