| 摘要 |
An arrangement for producing first to third effective addresses by processing an indirect designation processing instruction indicated by its code. An address register first memorizes, as the first effective address, an indirect descriptor address. An address register memorizes this latter portion as the second effective address instead of the first one. This makes the main memory produce a direct designation data descriptor comprising a direct designation indicating and a direct designation address portion. Meanwhile, a storing circuit stores the code and the first effective address in a first part of a buffer memory. The storing circuit stores this portion and the second effective address in the first part instead of the code and the first effective address. The address register now memorizes the direct designation address portion as the third effective address instead of the second one to make the main memory produce an operand datum. Meanwhile, the storing circuit is energized by the direct designation indicating portion and stores this portion and the third effective address in a second part of the buffer memory.
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