| 摘要 |
A digital frequency discrimination circuit includes an edge detector (170) coupled to receive a transmission signal (RD+, RD-) for producing an edge detected signal (171); an edge timer (180) including a shift register clocked by the clock signal (160) and having the edge detected signal as a data input, and a timeout determining subcircuit having a plurality of bits of the shift register coupled as edge detections inputs, for determining and providing a timeout signal (181) indicating whether any of the edge detection inputs represents an edge detection; and a state machine circuit (190) coupled to receive the clock signal, the edge detected signal, and the timeout signal for producing an unsquelch signal (150) indicating whether the transmission signal meets frequency discrimination requirements. |
