发明名称 |
PLL with stable phase discriminator. |
摘要 |
A PLL comprises a charge pump (14) with a current source (32) and a current sink (34) to control a VCO (12), and a phase discriminator (18) to compare a VCO's signal to a stable reference signal for controlling the charge pump. The phase discriminator includes a resettable D-flipflop (52) to provide the current source control signal and a resettable D-flipflop (54) to provide the current sink control signal. The reset signal keeps both sink and source temporarily alive to avoid a dead zone region. The reset signal is produced by a logical gate (56) under combined control of the sink and source control signals and, in addition, of the reference signal to enhance stability. <IMAGE> |
申请公布号 |
EP0599372(A1) |
申请公布日期 |
1994.06.01 |
申请号 |
EP19930203148 |
申请日期 |
1993.11.11 |
申请人 |
PHILIPS ELECTRONICS N.V.;FASELEC A.G. |
发明人 |
FOLMER, LAMBERT JOHAN HENDRIK |
分类号 |
H03D13/00;H03L7/089 |
主分类号 |
H03D13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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