| 摘要 |
The adverse effects of charge sharing in dynamic logic gates are mitigated. The dynamic logic gates have an inverting buffer for providing a gate output, an arming mechanism for precharging the inverting buffer input, and ladder logic for receiving a gate input and for discharging the inverting buffer input to ground. The ladder logic comprises a plurality of transistors connected in ladder-like manner. In a first embodiment, the interstitial space between parallel transistor gates in the ladder logic is reduced so as to minimize parasitic capacitances. In a second embodiment, the parasitic capacitance of at a converging node defined by at least three converging transistors is minimized by disposing the transistor gates adjacent one another so that the transistors share a common interstitial space with a region of each transistor gate adjacent a region of each of the other remaining gates. In a third embodiment, a precharger is disposed to inject charge at the converging node when the inverting buffer input is precharged by the arming mechanism. Finally, in a fourth embodiment, the plurality of transistors in the ladder logic are connected in a ladder-like manner exclusively to thereby define a plurality of mutually exclusive paths to ground.
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