High voltage CMOS circuit with NAND configured logic gates and a reduced number of N-MOS transistors requiring drain extension

摘要

In a CMOS logic circuit destined to function at a relatively high supply voltage such as to require the formation of graded diffusions in the structure of N-MOS transistors, a NAND configuration is used which comprises a staked pair of N-MOS transistors. This permits to restrict the number of graded diffusions to be formed in N-MOS structures only to the drain regions which are directly connected to an output node. In clocked CMOS circuitry where transfer transistors are normally used between gates, the advantages in terms of enhanced speed and ability of the circuit to be compacted by cutting the number of N-MOS structures necessarily provided with drain extension regions as in prior art circuits, are remarkable.