| 摘要 |
<p>A high performance Local Bus Peripheral Interface (LBPI) (3), which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer (73), a Read Ahead Counter (54), a Data Out Latch (61), and a Controlling State Machine (50) with a configuration Register (51). Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or snooping the peripheral device commands from the computer to intelligently predict the occurence of subsequent read data transfer commands. The Controlling State Machine also 'snoops' the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active.</p> |
